Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet
1–29
Timing Information
Timing Information
Figure 1–7 shows the configuration timing waveform when using an enhanced
configuration device.
Figure 1–7. Configuration Timing Waveform Using an Enhanced Configuration Device
nINIT_CONF or VCC/nCONFIG
tPOR
OE/nSTATUS
nCS/CONF_DONE
tCH
tDSU
tCL
DCLK
tOEZX
tDH
Byte0 Byte1 Byte2 Byte3
Byten
DATA[7..0]
(2)
tCO
User I/O
User Mode
Tri-State
Tri-State
INIT_DONE
Notes to Figure 1–7:
(1) The enhanced configuration device will drive DCLKlow after configuration.
(2) The enhanced configuration device will drive DATA[]high after configuration.
Table 1–14 defines the timing parameters when using the enhanced configuration
devices.
f
For more information about the flash memory (external flash interface) timing, refer
to the appropriate flash data sheet on the Altera website at www.altera.com.
■
■
■
For Micron flash-based EPC4, refer to the Micron MT28F400B3 Data Sheet Flash
Memory Used in EPC4 Devices at www.micron.com.
For Sharp flash-based EPC16, refer to the Sharp LHF16J06 Data Sheet Flash Memory
Used in EPC16 Devices at www.sharpsma.com.
For Intel flash-based EPC4 and EPC16, refer to Intel Flash 28F016B3 at
www.intel.com.
Table 1–14. Enhanced Configuration Device Configuration Parameters (Part 1 of 2)
Symbol
fDCLK
tDCLK
tHC
Parameter
DCLKfrequency
Condition
Min
—
15
6
Typ
—
—
—
—
—
—
—
—
—
—
Max
66.7
—
Unit
MHz
ns
40% duty cycle
DCLKperiod
—
DCLKduty cycle high time
DCLKduty cycle low time
OEto first DCLKdelay
40% duty cycle
—
ns
tLC
40% duty cycle
6
—
ns
tCE
—
—
—
—
—
—
40
40
(1)
277
277
60
—
ns
tOE
OEto first DATAavailable
DCLKrising edge to DATAchange
OEassert to DCLKdisable delay
OEassert to DATAdisable delay
DCLKrising edge to OE
—
ns
tOH
—
ns
tCF (2)
—
ns
t
DF (2)
RE (3)
—
ns
t
—
ns
© December 2009 Altera Corporation
Configuration Handbook (Complete Two-Volume Set)
ALTERA [ ALTERA CORPORATION ]
