1–28
Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet
IEEE Std. 1149.1 (JTAG) Boundary-Scan
IEEE Std. 1149.1 (JTAG) Boundary-Scan
The enhanced configuration device provides JTAG BST circuitry that complies with
the IEEE Std. 1149.1-1990 specification. JTAG boundary-scan testing can be performed
before or after configuration, but not during configuration.
Figure 1–6 shows the timing requirements for the JTAG signals.
Figure 1–6. JTAG Timing Waveforms
TMS
TDI
tJCP
tJCH
tJCL
tJPH
tJPSU
TCK
TDO
tJPZX
tJPCO
tJPXZ
tJSSU
tJSH
Signal
to be
Captured
tJSZX
tJSCO
tJSXZ
Signal
to be
Driven
Table 1–13 lists the timing parameters and values for the enhanced configuration
device.
Table 1–13. JTAG Timing Parameters and Values
Symbol Parameter
Min
100
50
50
20
45
—
—
—
20
45
—
—
—
Max
—
—
—
—
—
25
25
25
—
—
25
25
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tJCP
TCKclock period
tJCH
TCKclock high time
TCKclock low time
tJCL
tJPSU
tJPH
JTAG port setup time
JTAG port hold time
tJPCO
tJPZX
tJPXZ
tJSSU
tJSH
JTAG port clock output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
Capture register hold time
tJSCO
tJSZX
tJSXZ
Update register clock to output
Update register high-impedance to valid output
Update register valid output to high impedance
Configuration Handbook (Complete Two-Volume Set)
© December 2009 Altera Corporation
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