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EP1C6F256I8 参数 Datasheet PDF下载

EP1C6F256I8图片预览
型号: EP1C6F256I8
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列 [Cyclone FPGA Family]
分类和应用: 可编程逻辑时钟
文件页数/大小: 94 页 / 1066 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Cyclone FPGA Family Data Sheet  
Preliminary Information  
Figure 21. Single-Port Mode  
6 LAB Row  
Clocks  
RAM/ROM  
6
256 × 16  
512 × 8  
1,024 × 4  
2,048 × 2  
4,096 × 1  
data[ ]  
D
ENA  
Q
Data In  
To MultiTrack  
Interconnect  
Data Out  
D
Q
ENA  
address[ ]  
wren  
Address  
D
Q
ENA  
Write Enable  
outclken  
D
ENA  
Q
inclken  
inclock  
Write  
Pulse  
Generator  
outclock  
Cyclone devices provide a global clock network and up to two PLLs for a  
complete clock management solution.  
Global Clock  
Network &  
Phase-Locked  
Loops  
Global Clock Network  
There are four dedicated clock pins (CLK[3..0], two pins on the left side  
and two pins on the right side) that drive the global clock network, as  
shown in Figure 22. PLL outputs, logic array, and dual-purpose clock  
(DPCLK[7..0]) pins can also drive the global clock network.  
The eight global clock lines in the global clock network drive throughout  
the entire device. The global clock network can provide clocks for all  
resources within the device IOEs, LEs, and memory blocks. The global  
clock lines can also be used for control signals, such as clock enables and  
synchronous or asynchronous clears fed from the external pin, or DQS  
signals for DDR SDRAM or FCRAM interfaces. Internal logic can also  
drive the global clock network for internally generated global clocks and  
asynchronous clears, clock enables, or other control signals with large  
fanout. Figure 22 shows the various sources that drive the global clock  
network.  
34  
Altera Corporation  
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