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EP1C6F256I8 参数 Datasheet PDF下载

EP1C6F256I8图片预览
型号: EP1C6F256I8
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列 [Cyclone FPGA Family]
分类和应用: 可编程逻辑时钟
文件页数/大小: 94 页 / 1066 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Preliminary Information  
Cyclone FPGA Family Data Sheet  
When configured as RAM or ROM, the designer can use an initialization  
file to pre-load the memory contents.  
Two single-port memory blocks can be implemented in a single M4K  
block as long as each of the two independent block sizes is equal to or less  
than half of the M4K block size.  
The Quartus II software automatically implements larger memory by  
combining multiple M4K memory blocks. For example, two 256 × 16-bit  
RAM blocks can be combined to form a 256 × 32-bit RAM block. Memory  
performance does not degrade for memory blocks using the maximum  
number of words allowed. Logical memory blocks using less than the  
maximum number of words use physical blocks in parallel, eliminating  
any external control logic that would increase delays. To create a larger  
high-speed memory block, the Quartus II software automatically  
combines memory blocks with LE control logic.  
Parity Bit Support  
The M4K blocks support a parity bit for each byte. The parity bit, along  
with internal LE logic, can implement parity checking for error detection  
to ensure data integrity. Designers can also use parity-size data words to  
store user-specified control bits. Byte enables are also available for data  
input masking during write operations.  
Shift Register Support  
The designer can configure M4K memory blocks to implement shift  
registers for DSP applications such as pseudo-random number  
generators, multi-channel filtering, auto-correlation, and cross-correlation  
functions. These and other DSP applications require local data storage,  
traditionally implemented with standard flip-flops, which can quickly  
consume many logic cells and routing resources for large shift registers. A  
more efficient alternative is to use embedded memory as a shift register  
block, which saves logic cell and routing resources and provides a more  
efficient implementation with the dedicated circuitry.  
The size of a w × m × n shift register is determined by the input data width  
(w), the length of the taps (m), and the number of taps (n). The size of a  
w × m × n shift register must be less than or equal to the maximum number  
of memory bits in the M4K block (4,608 bits). The total number of shift  
register outputs (number of taps n × width w) must be less than the  
maximum data width of the M4K RAM block (×36). To create larger shift  
registers, multiple memory blocks are cascaded together.  
Altera Corporation  
25  
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