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EP1C6F256I8 参数 Datasheet PDF下载

EP1C6F256I8图片预览
型号: EP1C6F256I8
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列 [Cyclone FPGA Family]
分类和应用: 可编程逻辑时钟
文件页数/大小: 94 页 / 1066 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Cyclone FPGA Family Data Sheet  
Preliminary Information  
Figure 13. Simple Dual-Port & Single-Port Memory Configurations  
Simple Dual-Port Memory  
data[]  
rdaddress[]  
rden  
wraddress[]  
wren  
q[]  
inclock  
inclocken  
inaclr  
outclock  
outclocken  
outaclr  
Single-Port Memory (1)  
data[]  
address[]  
wren  
q[]  
outclock  
inclock  
inclocken  
inaclr  
outclocken  
outaclr  
Note to Figure 13:  
(1) Two single-port memory blocks can be implemented in a single M4K block as long  
as each of the two independent block sizes is equal to or less than half of the M4K  
block size.  
The memory blocks also enable mixed-width data ports for reading and  
writing to the RAM ports in dual-port RAM configuration. For example,  
the memory block can be written in ×1 mode at port A and read out in ×16  
mode from port B.  
The Cyclone memory architecture can implement fully synchronous RAM  
by registering both the input and output signals to the M4K RAM block.  
All M4K memory block inputs are registered, providing synchronous  
write cycles. In synchronous operation, the memory block generates its  
own self-timed strobe write enable (wren) signal derived from a global  
clock. In contrast, a circuit using asynchronous RAM must generate the  
RAM wrensignal while ensuring its data and address signals meet setup  
and hold time specifications relative to the wrensignal. The output  
registers can be bypassed. Pseudo-asynchronous reading is possible in the  
simple dual-port mode of M4K blocks by clocking the read enable and  
read address registers on the negative clock edge and bypassing the  
output registers.  
24  
Altera Corporation  
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