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EP1C6F256I8 参数 Datasheet PDF下载

EP1C6F256I8图片预览
型号: EP1C6F256I8
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列 [Cyclone FPGA Family]
分类和应用: 可编程逻辑时钟
文件页数/大小: 94 页 / 1066 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Cyclone FPGA Family Data Sheet  
Preliminary Information  
Figure 7. LE in Dynamic Arithmetic Mode  
LAB Carry-In  
Carry-In0  
sload  
sclear  
aload  
(LAB Wide)  
(LAB Wide) (LAB Wide)  
Carry-In1  
Register chain  
connection  
addnsub  
(LAB Wide)  
(1)  
ALD/PRE  
data1  
data2  
data3  
LUT  
ADATA  
D
Row, column, and  
direct link routing  
Q
LUT  
LUT  
LUT  
Row, column, and  
direct link routing  
ENA  
CLRN  
clock (LAB Wide)  
ena (LAB Wide)  
aclr (LAB Wide)  
Local routing  
LUT chain  
connection  
Register  
chain output  
Register Feedback  
Carry-Out0 Carry-Out1  
Note to Figure 7:  
(1) The addnsubsignal is tied to the carry input for the first LE of a carry chain only.  
Carry-Select Chain  
The carry-select chain provides a very fast carry-select function between  
LEs in dynamic arithmetic mode. The carry-select chain uses the  
redundant carry calculation to increase the speed of carry functions. The  
LE is configured to calculate outputs for a possible carry-in of 0 and carry-  
in of 1 in parallel. The carry-in0and carry-in1signals from a lower-  
order bit feed forward into the higher-order bit via the parallel carry chain  
and feed into both the LUT and the next portion of the carry chain. Carry-  
select chains can begin in any LE within an LAB.  
The speed advantage of the carry-select chain is in the parallel pre-  
computation of carry chains. Since the LAB carry-in selects the  
precomputed carry chain, not every LE is in the critical path. Only the  
propagation delays between LAB carry-in generation (LE 5 and LE 10) are  
now part of the critical path. This feature allows the Cyclone architecture  
to implement high-speed counters, adders, multipliers, parity functions,  
and comparators of arbitrary width.  
14  
Altera Corporation  
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