Preliminary Information
Cyclone FPGA Family Data Sheet
Figure 29. Column I/O Block Connection to the Interconnect
Column I/O
Block Contains
up to Three IOEs
Column I/O Block
21 Data &
Control Signals
from Logic Array (1)
IO_datain[2:0] &
comb_io_datain[2..0]
(2)
21
io_clk[5..0]
I/O Block
Local Interconnect
R4 Interconnects
LAB
LAB
LAB
LAB Local
C4 Interconnects
Interconnect
Notes to Figure 29:
(1) The 21 data and control signals consist of three data out lines, io_dataout[2..0], three output enables,
io_coe[2..0], three input clock enables, io_cce_in[2..0], three output clock enables, io_cce_out[2..0],
three clocks, io_cclk[2..0], three asynchronous clear signals, io_caclr[2..0], and three synchronous clear
signals, io_csclr[2..0].
(2) Each of the three IOEs in the column I/O block can have one io_dataininput (combinatorial or registered) and
one comb_io_datain(combinatorial) input.
Altera Corporation
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ALTERA [ ALTERA CORPORATION ]
