Preliminary Information
Cyclone FPGA Family Data Sheet
Figure 31. Control Signal Selection per IOE
Dedicated I/O
Clock [5..0]
io_coe
Local
Interconnect
io_csclr
Local
Interconnect
io_caclr
Local
Interconnect
io_cce_out
Local
Interconnect
io_cce_in
io_cclk
Local
Interconnect
ce_out
clk_out
sclr/preset
clk_in
ce_in
aclr/preset
oe
Local
Interconnect
In normal bidirectional operation, the designer can use the input register
for input data requiring fast setup times. The input register can have its
own clock input and clock enable separate from the OE and output
registers. The output register can be used for data requiring fast clock-to-
output performance. The OE register is available for fast clock-to-output
enable timing. The OE and output register share the same clock source
and the same clock enable source from the local interconnect in the
associated LAB, dedicated I/O clocks, or the column and row
interconnects. Figure 32 shows the IOE in bidirectional configuration.
Altera Corporation
49
ALTERA [ ALTERA CORPORATION ]
