Preliminary Information
Cyclone FPGA Family Data Sheet
Programmable Duty Cycle
The programmable duty cycle allows PLLs to generate clock outputs with
a variable duty cycle. This feature is supported on each PLL post-scale
counter (g0, g1, e). The duty cycle setting is achieved by a low- and high-
time count setting for the post-scale dividers. The Quartus II software uses
the frequency input and the required multiply or divide rate to determine
the duty cycle choices.
Control Signals
There are three control signals for clearing and enabling PLLs and their
outputs. The designer can use these signals to control PLL
resynchronization and the ability to gate PLL output clocks for low-power
applications.
The pllenablesignal enables and disables PLLs. When the pllenable
signal is low, the clock output ports are driven by ground and all the PLLs
go out of lock. When the pllenablesignal goes high again, the PLLs
relock and resynchronize to the input clocks. An input pin or LE output
can drive the pllenablesignal.
The aresetsignals are reset/resynchronization inputs for each PLL.
Cyclone devices can drive these input signals from input pins or from LEs.
When aresetis driven high, the PLL counters will reset, clearing the PLL
output and placing the PLL out of lock. When driven low again, the PLL
will resynchronize to its input as it relocks.
The pfdenasignals control the phase frequency detector (PFD) output
with a programmable gate. If you disable the PFD, the VCO will operate
at its last set value of control voltage and frequency with some drift, and
the system will continue running when the PLL goes out of lock or the
input clock disables. By maintaining the last locked frequency, the system
has time to store its current settings before shutting down. The designer
can either use their own control signal or gated locked status signals to
trigger the pfdenasignal.
For more information on Cyclone PLLs, see AN 251: Using PLLs in Cyclone
Devices.
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