Cyclone FPGA Family Data Sheet
Preliminary Information
Figure 32. Cyclone IOE in Bidirectional I/O Configuration
ioe_clk[5..0]
Column or Row
Interconect
OE
OE Register
PRN
D
Q
V
CCIO
clkout
ENA
Optional
PCI Clamp
CLRN
ce_out
V
CCIO
Programmable
Pull-Up
Resistor
aclr/prn
Chip-Wide Reset
Output
Pin Delay
Output Register
PRN
D
Q
ENA
Drive Strength Control
Open-Drain Output
Slew Control
sclr/preset
CLRN
comb_datain
data_in
Input Pin to
Logic Array Delay
Bus Hold
Input Pin to
Input Register Delay
or Input Pin to
Input Register
PRN
Logic Array Delay
D
Q
ENA
clkin
CLRN
ce_in
The Cyclone device IOE includes programmable delays to ensure zero
hold times, minimize setup times, or increase clock to output times.
50
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
