Preliminary Information
Cyclone FPGA Family Data Sheet
Figure 18. Input/Output Clock Mode in True Dual-Port Mode
Note (1)
6 LAB Row Clocks
6
6
Memory Block
256 × 16 (2)
512 × 8
1,024 × 4
2,048 × 2
A
B
dataA[ ]
dataB[ ]
Data In
Q
Q
Q
D
D
Q
Q
Q
Data In
ENA
ENA
4,096 × 1
byteenaA[ ]
byteenaB[ ]
Byte Enable A
Address A
D
D
Byte Enable B
Address B
ENA
ENA
addressA[ ]
wrenA
addressB[ ]
D
D
ENA
ENA
wrenB
Write/Read
Enable
Write/Read
Enable
Write
Pulse
Generator
Write
Pulse
Generator
Q
D
D
Q
clkenA
clockA
ENA
ENA
Data Out
Data Out
clkenB
clockB
D
Q
Q
D
ENA
ENA
qA[ ] qB[ ]
Note to Figure 18:
(1) All registers shown have asynchronous clear ports.
Altera Corporation
31
ALTERA [ ALTERA CORPORATION ]
