Preliminary Information
Cyclone FPGA Family Data Sheet
Figure 22. Global Clock Generation
Note (1)
DPCLK2
DPCLK3
Cyclone Device
Global Clock
Network
8
DPCLK1
DPCLK4
From logic
array
From logic
array
4
4
CLK0
PLL1
CLK2
PLL2
(2)
CLK1 (3)
CLK3 (3)
4
4
2
2
DPCLK0
DPCLK5
DPCLK7
DPCLK6
Notes to Figure 22:
(1) The EP1C3 device in the 100-pin TQFP package has five DPCLKpins (DPCLK2, DPCLK3, DPCLK4, DPCLK6, and
DPCLK7).
(2) EP1C3 devices only contain one PLL (PLL 1).
(3) The EP1C3 device in the 100-pin TQFP package does not have dedicated clock pins CLK1and CLK3.
Altera Corporation
35
ALTERA [ ALTERA CORPORATION ]
