Preliminary Information
Cyclone FPGA Family Data Sheet
Memory Configuration Sizes
The memory address depths and output widths can be configured as
4,096 × 1, 2,048 × 2, 1,024 × 4, 512 × 8 (or 512 × 9 bits), 256 × 16 (or 256 × 18
bits), and 128 x 32 (or 128 x 36 bits). The 128 x 32- or 36-bit configuration
is not available in the true dual-port mode. Mixed-width configurations
are also possible, allowing different read and write widths. Tables 6 and 7
summarize the possible M4K RAM block configurations.
Table 6. M4K RAM Block Configurations (Simple Dual-Port)
Read Port
Write Port
1K × 4 512 × 8 256 × 16 128 × 32 512 × 9 256 × 18 128 × 36
4K × 1
2K × 2
4K × 1
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
2K × 2
1K × 4
512 × 8
256 × 16
128 × 32
512 × 9
256 × 18
128 × 36
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Table 7. M4K RAM Block Configurations (True Dual-Port)
Port A
Port B
4K × 1
2K × 2
1K × 4
512 × 8
256 × 16 512 × 9
256 × 18
4K × 1
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
2K × 2
1K × 4
512 × 8
256 × 16
512 × 9
256 × 18
v
v
v
v
v
v
v
When the M4K RAM block is configured as a shift register block, the
designer can create a shift register up to 4,608 bits (w × m × n).
Altera Corporation
27
ALTERA [ ALTERA CORPORATION ]
