Cyclone FPGA Family Data Sheet
Preliminary Information
Independent Clock Mode
The M4K memory blocks implement independent clock mode for true
dual-port memory. In this mode, a separate clock is available for each port
(ports A and B). Clock A controls all registers on the port A side, while
clock B controls all registers on the port B side. Each port, A and B, also
supports independent clock enables and asynchronous clear signals for
port A and B registers. Figure 17 shows an M4K memory block in
independent clock mode.
Figure 17. Independent Clock Mode
Note (1)
6 LAB Row Clocks
Memory Block
256 ´ 16 (2)
512 ´ 8
1,024 ´ 4
2,048 ´ 2
A
B
6
6
dataA[ ]
dataB[ ]
Data In
Q
Q
D
D
ENA
Q
Q
Data In
ENA
4,096 ´ 1
byteenaA[ ]
byteenaB[ ]
Byte Enable A
Address A
D
D
Byte Enable B
Address B
ENA
ENA
addressA[ ]
wrenA
addressB[ ]
wrenB
Q
Q
D
D
Q
Q
ENA
ENA
Write/Read
Enable
Write/Read
Enable
D
D
Write
Pulse
Generator
Write
Pulse
Generator
clkenA
clockA
clkenB
clockB
ENA
ENA
Data Out
Data Out
D
Q
Q
D
ENA
ENA
qA[ ] qB[ ]
Note to Figure 17:
(1) All registers shown have asynchronous clear ports.
Input/Output Clock Mode
Input/output clock mode can be implemented for both the true and
simple dual-port memory modes. On each of the two ports, A or B, one
clock controls all registers for inputs into the memory block: data input,
wren, and address. The other clock controls the block’s data output
registers. Each memory block port, A or B, also supports independent
clock enables and asynchronous clear signals for input and output
registers. Figures 18 and 19 show the memory block in input/output clock
mode.
30
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
