Preliminary Information
Cyclone FPGA Family Data Sheet
The Cyclone embedded memory consists of columns of M4K memory
blocks. EP1C3 and EP1C6 devices have one column of M4K blocks, while
EP1C12 and EP1C20 devices have two columns (see Table 1 on page 1 for
total RAM bits per density). Each M4K block can implement various types
of memory with or without parity, including true dual-port, simple dual-
port, and single-port RAM, ROM, and FIFO buffers. The M4K blocks
support the following features:
Embedded
Memory
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■
■
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4,608 RAM bits
200 MHz performance
True dual-port memory
Simple dual-port memory
Single-port memory
Byte enable
Parity bits
Shift register
FIFO buffer
ROM
Mixed clock mode
Memory Modes
The M4K memory blocks include input registers that synchronize writes
and output registers to pipeline designs and improve system
performance. M4K blocks offer a true dual-port mode to support any
combination of two-port operations: two reads, two writes, or one read
and one write at two different clock frequencies. Figure 12 shows true
dual-port memory.
Figure 12. True Dual-Port Memory Configuration
A
B
dataA[]
dataB[]
addressA[]
wrenA
addressB[]
wrenB
clockA
clockenA
qA[]
clockB
clockenB
qB[]
aclrA
aclrB
In addition to true dual-port memory, the M4K memory blocks support
simple dual-port and single-port RAM. Simple dual-port memory
supports a simultaneous read and write. Single-port memory supports
non-simultaneous reads and writes. Figure 13 shows these different M4K
RAM memory port configurations.
Altera Corporation
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ALTERA [ ALTERA CORPORATION ]
