Timing Model
Table 4–51. Cyclone Maximum Output Clock Rate for Row Pins
-6 Speed
Grade
-7 Speed
Grade
-8 Speed
Grade
I/O Standard
Unit
LVTTL
2.5 V
1.8 V
1.5 V
296
381
286
219
367
169
160
160
131
66
285
366
277
208
356
166
151
151
123
66
273
349
267
195
343
162
146
142
115
66
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
LVCMOS
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
3.3-V PCI (1)
LVDS
320
303
275
Note to Tables 4–50 through 4–51:
(1) EP1C3 devices do not support the PCI I/O standard. These parameters are only
available on row I/O pins.
PLL Timing
Table 4–52 describes the Cyclone FPGA PLL specifications.
Table 4–52. Cyclone PLL Specifications (Part 1 of 2)
Symbol
Parameter
Min
Max
Unit
fIN
Input frequency (-6 speed
15.625
464
MHz
grade)
Input frequency (-7 speed
grade)
15.625
15.625
40.00
428
387
60
MHz
MHz
Input frequency (-8 speed
grade)
f
t
IN DUTY
IN JITTER
Input clock duty cycle
Input clock period jitter
%
ps
200
f
OUT_EXT (external PLL
PLL output frequency
(-6 speed grade)
15.625
15.625
15.625
320
320
275
MHz
MHz
MHz
clock output)
PLL output frequency
(-7 speed grade)
PLL output frequency
(-8 speed grade)
Altera Corporation
January 2007
4–29
Preliminary
ALTERA [ ALTERA CORPORATION ]
