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EP1C4F324I7ES 参数 Datasheet PDF下载

EP1C4F324I7ES图片预览
型号: EP1C4F324I7ES
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列数据手册 [Cyclone FPGA Family Data Sheet]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 104 页 / 1360 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Cyclone Device Handbook, Volume 1  
Table 4–45. Cyclone I/O Standard Output Delay Adders for Slow Slew Rate on Row Pins (Part 2 of 2)  
-6 Speed Grade  
-7 Speed Grade  
-8 Speed Grade  
I/O Standard  
Unit  
Min  
Max  
Min  
Max  
Min  
Max  
SSTL-3 class I  
1,390  
989  
1,598  
1,137  
2,259  
1,945  
922  
1,807  
1,285  
2,554  
2,199  
1,042  
ps  
ps  
ps  
ps  
ps  
SSTL-3 class II  
SSTL-2 class I  
SSTL-2 class II  
LVDS  
1,965  
1,692  
802  
Note to Tables 4–40 through 4–45:  
(1) EP1C3 devices do not support the PCI I/O standard.  
Tables 4–46 through 4–47 show the adder delays for the IOE  
programmable delays. These delays are controlled with the Quartus II  
software options listed in the Parameter column.  
Table 4–46. Cyclone IOE Programmable Delays on Column Pins  
-6 Speed Grade -7 Speed Grade  
-8 Speed Grade  
Parameter  
Setting  
Unit  
Min  
Max  
Min  
Max  
Min  
Max  
Decrease input delay to Off  
internal cells  
155  
2,122  
2,639  
3,057  
155  
178  
2,543  
3,034  
3,515  
178  
201  
2,875  
3,430  
3,974  
201  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
Small  
Medium  
Large  
On  
Decrease input delay to Off  
input register  
0
0
0
On  
3,057  
0
3,515  
0
3,974  
0
Increase delay to output Off  
pin  
On  
552  
634  
717  
4–26  
Preliminary  
Altera Corporation  
January 2007  
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