Timing Model
Table 4–47. Cyclone IOE Programmable Delays on Row Pins
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Parameter
Setting
Unit
Min
Max
Min
Max
Min
Max
Decrease input delay to
internal cells
Off
154
2,212
2,639
3,057
154
177
2,543
3,034
3,515
177
200
2,875
3,430
3,974
200
ps
ps
ps
ps
ps
ps
ps
ps
ps
Small
Medium
Large
On
Decrease input delay to input Off
register
0
0
0
On
3,057
0
3,515
0
3,974
0
Increase delay to output pin Off
On
556
639
722
Note to Table 4–47:
(1) EPC1C3 devices do not support the PCI I/O standard
Maximum Input & Output Clock Rates
Tables 4–48 and 4–49 show the maximum input clock rate for column and
row pins in Cyclone devices.
Table 4–48. Cyclone Maximum Input Clock Rate for Column Pins
-6 Speed
Grade
-7 Speed
Grade
-8 Speed
Grade
I/O Standard
Unit
LVTTL
2.5 V
1.8 V
1.5 V
464
392
387
387
405
405
414
464
473
567
428
302
311
320
374
356
365
428
432
549
387
207
252
243
333
293
302
396
396
531
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
LVCMOS
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
LVDS
Altera Corporation
January 2007
4–27
Preliminary
ALTERA [ ALTERA CORPORATION ]
