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EP1C4F324I7ES 参数 Datasheet PDF下载

EP1C4F324I7ES图片预览
型号: EP1C4F324I7ES
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列数据手册 [Cyclone FPGA Family Data Sheet]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 104 页 / 1360 K
品牌: ALTERA [ ALTERA CORPORATION ]
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IEEE Std. 1149.1 (JTAG) Boundary Scan Support  
The Cyclone device instruction register length is 10 bits and the  
USERCODE register length is 32 bits. Tables 3–2 and 3–3 show the  
boundary-scan register length and device IDCODE information for  
Cyclone devices.  
Table 3–2. Cyclone Boundary-Scan Register Length  
Device  
Boundary-Scan Register Length  
EP1C3  
EP1C4  
EP1C6  
EP1C12  
EP1C20  
339  
930  
582  
774  
930  
Table 3–3. 32-Bit Cyclone Device IDCODE  
IDCODE (32 bits) (1)  
Device  
Manufacturer Identity  
Version (4 Bits)  
Part Number (16 Bits)  
LSB (1 Bit) (2)  
(11 Bits)  
EP1C3  
EP1C4  
EP1C6  
EP1C12  
EP1C20  
0000  
0000  
0000  
0000  
0000  
0010 0000 1000 0001  
0010 0000 1000 0101  
0010 0000 1000 0010  
0010 0000 1000 0011  
0010 0000 1000 0100  
000 0110 1110  
000 0110 1110  
000 0110 1110  
000 0110 1110  
000 0110 1110  
1
1
1
1
1
Notes to Table 3–3:  
(1) The most significant bit (MSB) is on the left.  
(2) The IDCODE’s least significant bit (LSB) is always 1.  
Altera Corporation  
January 2007  
3–3  
Preliminary  
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