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EP1C4F324I7ES 参数 Datasheet PDF下载

EP1C4F324I7ES图片预览
型号: EP1C4F324I7ES
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列数据手册 [Cyclone FPGA Family Data Sheet]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 104 页 / 1360 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Cyclone Device Handbook, Volume 1  
Table 3–1. Cyclone JTAG Instructions (Part 2 of 2)  
JTAG Instruction  
Instruction Code  
Description  
00 0000 0111  
Selects the 32-bit USERCODE register and places it between the  
TDI and TDO pins, allowing the USERCODE to be serially shifted  
out of TDO.  
USERCODE  
00 0000 0110  
00 0000 1011  
Selects the IDCODE register and places it between TDI and TDO,  
allowing the IDCODE to be serially shifted out of TDO.  
IDCODE  
Places the 1-bit bypass register between the TDI and TDO pins,  
which allows the BST data to pass synchronously through selected  
devices to adjacent devices during normal device operation, while  
tri-stating all of the I/O pins.  
HIGHZ(1)  
00 0000 1010  
Places the 1-bit bypass register between the TDI and TDO pins,  
which allows the BST data to pass synchronously through selected  
devices to adjacent devices during normal device operation while  
holding I/O pins to a state defined by the data in the boundary-scan  
register.  
CLAMP(1)  
ICR instructions  
Used when configuring a Cyclone device via the JTAG port with a  
MasterBlasterTM or ByteBlasterMVTM download cable, or when  
using a Jam File or Jam Byte-Code File via an embedded  
processor.  
00 0000 0001  
00 0000 1101  
PULSE_NCONFIG  
CONFIG_IO  
Emulates pulsing the nCONFIGpin low to trigger reconfiguration  
even though the physical pin is unaffected.  
Allows configuration of I/O standards through the JTAG chain for  
JTAG testing. Can be executed before, after, or during  
configuration. Stops configuration if executed during configuration.  
Once issued, the CONFIG_IOinstruction will hold nSTATUSlow  
to reset the configuration device. nSTATUSis held low until the  
device is reconfigured.  
SignalTap II  
instructions  
Monitors internal device operation with the SignalTap II embedded  
logic analyzer.  
Note to Table 3–1:  
(1) Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST.  
In the Quartus II software, there is an Auto Usercode feature where you  
can choose to use the checksum value of a programming file as the JTAG  
user code. If selected, the checksum is automatically loaded to the  
USERCODE register. Choose Assignments > Device > Device and Pin  
Options > General. Turn on Auto Usercode.  
3–2  
Preliminary  
Altera Corporation  
January 2007  
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