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EP1C20F400C7ES 参数 Datasheet PDF下载

EP1C20F400C7ES图片预览
型号: EP1C20F400C7ES
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列数据手册 [Cyclone FPGA Family Data Sheet]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 104 页 / 1353 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Features  
Cyclone devices are available in quad flat pack (QFP) and space-saving  
FineLine® BGA packages (see Table 1–2 through 1–3).  
Table 1–2. Cyclone Package Options & I/O Pin Counts  
100-Pin TQFP 144-Pin TQFP 240-PinPQFP  
256-Pin  
324-Pin  
400-Pin  
Device  
(1)  
(1), (2)  
(1)  
FineLine BGA FineLine BGA FineLine BGA  
EP1C3  
65  
104  
EP1C4  
EP1C6  
EP1C12  
EP1C20  
249  
301  
301  
98  
185  
173  
185  
185  
249  
233  
Notes to Table 1–2:  
(1) TQFP: thin quad flat pack.  
PQFP: plastic quad flat pack.  
(2) Cyclone devices support vertical migration within the same package (i.e., designers can migrate between the  
EP1C3 device in the 144-pin TQFP package and the EP1C6 device in the same package)  
Vertical migration means you can migrate a design from one device to  
another that has the same dedicated pins, JTAG pins, and power pins, and  
are subsets or supersets for a given package across device densities. The  
largest density in any package has the highest number of power pins; you  
must use the layout for the largest planned density in a package to  
provide the necessary power pins for migration.  
For I/O pin migration across densities, cross-reference the available I/O  
pins using the device pin-outs for all planned densities of a given package  
type to identify which I/O pins can be migrated. The Quartus® II  
software can automatically cross-reference and place all pins for you  
when given a device migration list. If one device has power or ground  
pins, but these same pins are user I/O on a different device that is in the  
migration path,the Quartus II software ensures the pins are not used as  
user I/O in the Quartus II software. Ensure that these pins are connected  
to the appropriate plane on the board. The Quartus II software reserves  
I/O pins as power pins as necessary for layout with the larger densities  
in the same package having more power pins.  
Altera Corporation  
January 2007  
1–3  
Preliminary  
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