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EP1C20F400C7ES 参数 Datasheet PDF下载

EP1C20F400C7ES图片预览
型号: EP1C20F400C7ES
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列数据手册 [Cyclone FPGA Family Data Sheet]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 104 页 / 1353 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Cyclone Device Handbook, Volume 1  
The Cyclone device family offers the following features:  
Features  
2,910 to 20,060 LEs, see Table 1–1  
Up to 294,912 RAM bits (36,864 bytes)  
Supports configuration through low-cost serial configuration device  
Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards  
Support for 66- and 33-MHz, 64- and 32-bit PCI standard  
High-speed (640 Mbps) LVDS I/O support  
Low-speed (311 Mbps) LVDS I/O support  
311-Mbps RSDS I/O support  
Up to two PLLs per device provide clock multiplication and phase  
shifting  
Up to eight global clock lines with six clock resources available per  
logic array block (LAB) row  
Support for external memory, including DDR SDRAM (133 MHz),  
FCRAM, and single data rate (SDR) SDRAM  
Support for multiple intellectual property (IP) cores, including  
®
®
Altera MegaCore functions and Altera Megafunctions Partners  
SM  
Program (AMPP ) megafunctions.  
Table 1–1. Cyclone Device Features  
Feature  
EP1C3  
EP1C4  
EP1C6  
EP1C12  
EP1C20  
LEs  
2,910  
13  
4,000  
17  
5,980  
20  
12,060  
52  
20,060  
64  
M4K RAM blocks (128 × 36 bits)  
Total RAM bits  
59,904  
1
78,336  
2
92,160  
2
239,616  
2
294,912  
2
PLLs  
Maximum user I/O pins (1)  
104  
301  
185  
249  
301  
Note to Table 1–1:  
(1) This parameter includes global clock pins.  
1–2  
Preliminary  
Altera Corporation  
January 2007  
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