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EP1C20F400C7ES 参数 Datasheet PDF下载

EP1C20F400C7ES图片预览
型号: EP1C20F400C7ES
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列数据手册 [Cyclone FPGA Family Data Sheet]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 104 页 / 1353 K
品牌: ALTERA [ ALTERA CORPORATION ]
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1. Introduction  
C51001-1.4  
The Cyclone® field programmable gate array family is based on a 1.5-V,  
0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic  
elements (LEs) and up to 288 Kbits of RAM. With features like phase-  
locked loops (PLLs) for clocking and a dedicated double data rate (DDR)  
interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory  
requirements, Cyclone devices are a cost-effective solution for data-path  
applications. Cyclone devices support various I/O standards, including  
LVDS at data rates up to 640 megabits per second (Mbps), and 66- and  
33-MHz, 64- and 32-bit peripheral component interconnect (PCI), for  
interfacing with and supporting ASSP and ASIC devices. Altera also  
offers new low-cost serial configuration devices to configure Cyclone  
devices.  
Introduction  
The following shows the main sections in the Cyclone FPGA Family Data  
Sheet:  
Section  
Page  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2  
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1  
Logic Array Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3  
Logic Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5  
MultiTrack Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12  
Embedded Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18  
Global Clock Network & Phase-Locked Loops. . . . . . . . . . . 2–29  
I/O Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–39  
Power Sequencing & Hot Socketing . . . . . . . . . . . . . . . . . . . . 2–55  
IEEE Std. 1149.1 (JTAG) Boundary Scan Support. . . . . . . . . . 3–1  
SignalTap II Embedded Logic Analyzer . . . . . . . . . . . . . . . . . 3–5  
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5  
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1  
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8  
Timing Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9  
Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1  
Device Pin-Outs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1  
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1  
Altera Corporation  
January 2007  
1–1  
Preliminary  
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