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EP1C20F400C7ES 参数 Datasheet PDF下载

EP1C20F400C7ES图片预览
型号: EP1C20F400C7ES
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列数据手册 [Cyclone FPGA Family Data Sheet]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 104 页 / 1353 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Logic Array Blocks  
Each LAB consists of 10 LEs, LE carry chains, LAB control signals, a local  
interconnect, look-up table (LUT) chain, and register chain connection  
lines. The local interconnect transfers signals between LEs in the same  
LAB. LUT chain connections transfer the output of one LE's LUT to the  
adjacent LE for fast sequential LUT connections within the same LAB.  
Register chain connections transfer the output of one LE's register to the  
adjacent LE's register within an LAB. The Quartus® II Compiler places  
associated logic within an LAB or adjacent LABs, allowing the use of  
local, LUT chain, and register chain connections for performance and area  
efficiency. Figure 2–2 details the Cyclone LAB.  
Logic Array  
Blocks  
Figure 2–2. Cyclone LAB Structure  
Row Interconnect  
Column Interconnect  
Direct link  
interconnect from  
adjacent block  
Direct link  
interconnect from  
adjacent block  
Direct link  
Direct link  
interconnect to  
adjacent block  
interconnect to  
adjacent block  
LAB  
Local Interconnect  
LAB Interconnects  
The LAB local interconnect can drive LEs within the same LAB. The LAB  
local interconnect is driven by column and row interconnects and LE  
outputs within the same LAB. Neighboring LABs, PLLs, and M4K RAM  
blocks from the left and right can also drive an LAB's local interconnect  
through the direct link connection. The direct link connection feature  
minimizes the use of row and column interconnects, providing higher  
Altera Corporation  
January 2007  
2–3  
Preliminary  
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