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EP1C20F400C7ES 参数 Datasheet PDF下载

EP1C20F400C7ES图片预览
型号: EP1C20F400C7ES
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列数据手册 [Cyclone FPGA Family Data Sheet]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 104 页 / 1353 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Logic Elements  
With the LAB-wide addnsubcontrol signal, a single LE can implement a  
one-bit adder and subtractor. This saves LE resources and improves  
performance for logic functions such as DSP correlators and signed  
multipliers that alternate between addition and subtraction depending  
on data.  
The LAB row clocks [5..0] and LAB local interconnect generate the LAB-  
wide control signals. The MultiTrackTM interconnect's inherent low skew  
allows clock and control signal distribution in addition to data. Figure 2–4  
shows the LAB control signal generation circuit.  
Figure 2–4. LAB-Wide Control Signals  
Dedicated  
LAB Row  
Clocks  
6
Local  
Interconnect  
Local  
Interconnect  
Local  
Interconnect  
Local  
Interconnect  
Local  
Interconnect  
labclkena2  
labclkena1  
syncload  
labclr2  
addnsub  
Local  
Interconnect  
labclk1  
labclk2  
asyncload  
or labpre  
labclr1  
synclr  
The smallest unit of logic in the Cyclone architecture, the LE, is compact  
and provides advanced features with efficient logic utilization. Each LE  
contains a four-input LUT, which is a function generator that can  
implement any function of four variables. In addition, each LE contains a  
programmable register and carry chain with carry select capability. A  
single LE also supports dynamic single bit addition or subtraction mode  
selectable by an LAB-wide control signal. Each LE drives all types of  
interconnects: local, row, column, LUT chain, register chain, and direct  
link interconnects. See Figure 2–5.  
Logic Elements  
Altera Corporation  
January 2007  
2–5  
Preliminary  
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