欢迎访问ic37.com |
会员登录 免费注册
发布采购

EP1C20F400C7ES 参数 Datasheet PDF下载

EP1C20F400C7ES图片预览
型号: EP1C20F400C7ES
PDF下载: 下载PDF文件 查看货源
内容描述: 气旋FPGA系列数据手册 [Cyclone FPGA Family Data Sheet]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 104 页 / 1353 K
品牌: ALTERA [ ALTERA CORPORATION ]
 浏览型号EP1C20F400C7ES的Datasheet PDF文件第11页浏览型号EP1C20F400C7ES的Datasheet PDF文件第12页浏览型号EP1C20F400C7ES的Datasheet PDF文件第13页浏览型号EP1C20F400C7ES的Datasheet PDF文件第14页浏览型号EP1C20F400C7ES的Datasheet PDF文件第16页浏览型号EP1C20F400C7ES的Datasheet PDF文件第17页浏览型号EP1C20F400C7ES的Datasheet PDF文件第18页浏览型号EP1C20F400C7ES的Datasheet PDF文件第19页  
Logic Elements  
Dynamic Arithmetic Mode  
The dynamic arithmetic mode is ideal for implementing adders, counters,  
accumulators, wide parity functions, and comparators. An LE in dynamic  
arithmetic mode uses four 2-input LUTs configurable as a dynamic  
adder/subtractor. The first two 2-input LUTs compute two summations  
based on a possible carry-in of 1 or 0; the other two LUTs generate carry  
outputs for the two chains of the carry select circuitry. As shown in  
Figure 2–7, the LAB carry-in signal selects either the carry-in0or  
carry-in1chain. The selected chain's logic level in turn determines  
which parallel sum is generated as a combinatorial or registered output.  
For example, when implementing an adder, the sum output is the  
selection of two possible calculated sums:  
data1 + data2 + carry-in0  
or  
data1 + data2 + carry-in1  
The other two LUTs use the data1and data2signals to generate two  
possible carry-out signalsone for a carry of 1 and the other for a carry of  
0. The carry-in0signal acts as the carry select for the carry-out0  
output and carry-in1acts as the carry select for the carry-out1  
output. LEs in arithmetic mode can drive out registered and unregistered  
versions of the LUT output.  
The dynamic arithmetic mode also offers clock enable, counter enable,  
synchronous up/down control, synchronous clear, synchronous load,  
and dynamic adder/subtractor options. The LAB local interconnect data  
inputs generate the counter enable and synchronous up/down control  
signals. The synchronous clear and synchronous load options are LAB-  
wide signals that affect all registers in the LAB. The Quartus II software  
automatically places any registers that are not used by the counter into  
other LABs. The addnsubLAB-wide signal controls whether the LE acts  
as an adder or subtractor.  
Altera Corporation  
January 2007  
2–9  
Preliminary  
 复制成功!