2–8
Chapter 2: Arria GX Architecture
Transceivers
Figure 2–7 shows the serializer block diagram.
Figure 2–7. Serializer
D9
D8
D7
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D6
10
D5
8B/10B
From
Encoder
D4
D3
D2
D1
D0
To Transmitter
Output Buffer
Low-speed parallel clock
High-speed serial clock
CMU
Central /
Local Clock
Divider
Transmitter Buffer
The Arria GX transceiver buffers support the 1.2- and 1.5-V PCML I/O standard at
rates up to 3.125 Gbps. The common mode voltage (VCM) of the output driver may be
set to 600 or 700 mV.
f
For more information about the Arria GX transceiver buffers, refer to the Arria GX
Transceiver Architecture chapter.
The output buffer, as shown in Figure 2–8, is directly driven by the high-speed data
serializer and consists of a programmable output driver, a programmable
pre-emphasis circuit, and OCT circuitry.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
