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EP1AGX50DF1152I6N 参数 Datasheet PDF下载

EP1AGX50DF1152I6N图片预览
型号: EP1AGX50DF1152I6N
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内容描述: 第一节的Arria GX器件数据手册 [Section I. Arria GX Device Data Sheet]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 234 页 / 3509 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 2: Arria GX Architecture  
2–11  
Transceivers  
The receiver has 100-on-chip differential termination (RD OCT) for different  
protocols, as shown in Figure 2–11. You can disable the receiver’s internal termination  
if external terminations and biasing are provided. The receiver and transmitter  
differential termination method can be set independently of each other.  
Figure 2–11. Receiver Input Buffer  
100-Ω  
Termination  
Input  
Pins  
Programmable  
Equalizer  
Differential  
Input  
Buffer  
If a design uses external termination, the receiver must be externally terminated and  
biased to 0.85 V or 1.2 V. Figure 2–12 shows an example of an external termination and  
biasing circuit.  
Figure 2–12. External Termination and Biasing Circuit  
Receiver External Termination  
and Biasing  
Arria GX Device  
V
DD  
50-W  
Termination  
Resistance  
R1  
C1  
Receiver  
R1/R2 = 1K  
´ {R2/(R1 + R 2)} = 0.85/1.2 V  
RXIP  
V
R2  
DD  
RXIN  
Receiver External Termination  
and Biasing  
Transmission  
Line  
Programmable Equalizer  
The Arria GX receivers provide a programmable receiver equalization feature to  
compensate for the effects of channel attenuation for high-speed signaling. PCB traces  
carrying these high-speed signals have low-pass filter characteristics. Impedance  
mismatch boundaries can also cause signal degradation. Equalization in the receiver  
diminishes the lossy attenuation effects of the PCB at high frequencies.  
© December 2009 Altera Corporation  
Arria GX Device Handbook, Volume 1  
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