2–6
Chapter 2: Arria GX Architecture
Transceivers
Figure 2–5 shows byte serializer input and output. datain[15:0]is the input to the
byte serializer from the transmitter phase compensation FIFO; dataout[7:0]is the
output of the byte serializer.
Figure 2–5. Byte Serializer Operation (Note 1)
D1
D2
D3
datain[15:0]
dataout[7:0]
{8'h00,8'h01}
{8'h02,8'h03}
xxxx
D1LSByte
D1MSByte
D2LSByte
D2MSByte
xxxxxxxxxx
xxxxxxxxxx
8'h01
8'h00
8'h03
8'h02
Note to Figure 2–5:
(1) datainmay be 16 or 20 bits. dataoutmay be 8 or 10 bits.
8B/10B Encoder
The 8B/10B encoder block is used in all supported functional modes. The 8B/10B
encoder block takes in 8-bit data from the byte serializer or the transmitter phase
compensation FIFO buffer. It generates a 10-bit code group with proper running
disparity from the 8-bit character and a 1-bit control identifier (tx_ctrlenable).
When tx_ctrlenableis low, the 8-bit character is encoded as data code group
(Dx.y). When tx_ctrlenableis high, the 8-bit character is encoded as a control
code group (Kx.y). The 10-bit code group is fed to the serializer. The 8B/10B encoder
conforms to the IEEE 802.3 1998 edition standard.
f
For additional information regarding 8B/10B encoding rules, refer to the Specifications
and Additional Information chapter.
Figure 2–6 shows the 8B/10B conversion format.
Figure 2–6. 8B/10B Encoder
7
6
5
F
4
3
2
1
0
Ctrl
H
G
E
D
C
B
A
8B-10B Conversion
j
h
g
f
i
e
4
d
3
c
b
a
0
9
8
7
6
5
2
1
MSB
LSB
During reset (tx_digitalreset), the running disparity and data registers are
cleared and the 8B/10B encoder continously outputs a K28.5 pattern from the
RD-column. After out of reset, the 8B/10B encoder starts with a negative disparity
(RD-) and transmits three K28.5 code groups for synchronizing before it starts
encoding the input data or control character.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
