Chapter 4: DC and Switching Characteristics
4–87
Maximum Input and Output Clock Toggle Rate
Table 4–101 lists IOE programmable delays.
Table 4–101. Arria GX IOE Programmable Delay on Column Pins
Fast Model
Industrial Commercial
Min Max Min Max
–6 Speed Grade
Available
Settings
Parameter
Paths Affected
Units
Min
Max
Offset
Offset Offset Offset Offset Offset
Input delay
from pin to
internal cells
Pad to I/O dataout to
core
8
64
2
0
0
0
1.781
2.053
0.332
0
0
0
1.781
2.053
0.332
0
0
0
4.132
4.697
0.717
ns
ns
ns
Input delay
from pin to
input register
Pad to I/O input register
Delay from
output
I/O output register to
pad
register to
output pin
Output
enable pin
delay
txz/tzx
2
0
0.32
0
0.32
0
0.693
ns
Maximum Input and Output Clock Toggle Rate
Maximum clock toggle rate is defined as the maximum frequency achievable for a
clock type signal at an I/O pin. The I/O pin can be a regular I/O pin or a dedicated
clock I/O pin.
The maximum clock toggle rate is different from the maximum data bit rate. If the
maximum clock toggle rate on a regular I/O pin is 300 MHz, the maximum data bit
rate for dual data rate (DDR) could be potentially as high as 600 Mbps on the same
I/O pin.
Table 4–105, Table 4–106, and Table 4–107 provide output toggle rates at the default
capacitive loading. Use the Quartus II software to obtain output toggle rates at loads
different from the default capacitive loading.
Table 4–102 shows the maximum input clock toggle rates for Arria GX device column
I/O pins.
Table 4–102. Arria GX Maximum Input Toggle Rate for Column I/O Pins
I/O Standards
3.3-V LVTTL
–6 Speed Grade
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
420
420
420
420
420
467
467
467
3.3-V LVCMOS
2.5 V
1.8 V
1.5 V
SSTL-2 CLASS I
SSTL-2 CLASS II
SSTL-18 CLASS I
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
