4–86
Chapter 4: DC and Switching Characteristics
IOE Programmable Delay
Table 4–99. Arria GX Performance Notes
Resources Used
Performance
Applications
TriMatrix
Memory Blocks
ALUTs
DSP Blocks
–6 Speed Grade
9 x 9-bit
multiplier
0
0
0
0
0
0
0
0
1
335.35
18 x 18-bit
multiplier
0
0
0
0
0
0
2
4
8
8
8
4
285.0
335.35
174.4
285.0
163.0
163.0
18 x 18-bit
multiplier
DSP block
36 x 36-bit
multiplier
36 x 36-bit
multiplier
18-bit 4-tap FIR
filter
8-bit 16-tap
Larger Designs
parallel FIR filter
IOE Programmable Delay
For IOE programmable delay, refer to Table 4–100 through Table 4–101.
Table 4–100 lists IOE programmable delays.
Table 4–100. Arria GX IOE Programmable Delay on Row Pins
Fast Model
Industrial Commercial
–6 Speed Grade
Available
Settings
Parameter
Paths Affected
Units
Min
Max
Offset
Min
Offset
Max
Offset
Min
Max
Offset
Offset
Offset
Input delay
from pin to
internal cells
Pad to I/O dataout
to core
8
64
2
0
1.782
0
1.782
2.054
0.332
0
0
0
4.124
4.689
0.717
ns
ns
ns
Input delay
from pin to
input register
Pad to I/O input
register
0
0
2.054
0.332
0
0
Delay from I/O output register
output
register to
output pin
to pad
txz/tzx
Output
enable pin
delay
2
0
0.32
0
0.32
0
0.693
ns
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
