Classic EPLD Family Data Sheet
Figure 5. Classic Switching Waveforms
t
R
and t
F
< 3 ns.
Inputs are driven at 3 V
for a logic high and
0 V for a logic low.
All timing characteristics
are measured at 1.5 V.
Input Mode
t
IO
I/O Pin
t
PD1
=
t
IN
+ t
LAD
+ t
OD
t
PD2
=
t
IO
+ t
IN
+ t
LAD
+ t
OD
t
IN
Input Pin
t
LAD
Logic Array Input
t
CLR
Logic Array Output
t
OD
Output Pin
Global Clock Mode
t
R
Global Clock Pin
t
CH
t
CL
t
F
t
IN
Global Clock at Register
t
ICS
t
SU
Data from Logic Array
t
H
Array Clock Mode
t
R
Clock Pin
t
ACH
t
ACL
t
F
t
IN
Clock into Logic Array
t
IC
Clock from Logic Array
t
ASU
Data from Logic Array
t
AH
t
FD
Register Output to Logic Array
Output Mode
Clock from Logic Array
t
OD
Data from Logic Array
t
XZ
Output Pin
t
ZX
High-Impedance
Tri-State
752
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
