EP610 EPLD
■
High-performance, 16-macrocell Classic EPLD
Features
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–
–
Combinatorial speeds with tPD as fast as 10 ns
Counter frequencies of up to 100 MHz
Pipelined data rates of up to 125 MHz
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■
Programmable I/O architecture with up to 20 inputs or 16 outputs
and 2 clock pins
EP610 and EP610I devices are pin-, function-, and programming
file-compatible
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■
Programmable clock option for independent clocking of all registers
Macrocells individually programmable as D, T, JK, or SR flipflops, or
for combinatorial operation
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Available in the following packages (see Figure 7):
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–
24-pin small-outline integrated circuit (plastic SOIC only)
24-pin ceramic and plastic dual in-line package (CerDIP and
PDIP)
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28-pin plastic J-lead chip carrier (PLCC)
Figure 7. EP610 Package Pin-Out Diagrams
Package outlines not drawn to scale. Windows in ceramic packages only.
1
24
23
22
21
20
19
18
17
16
15
14
13
CLK1
INPUT
I/O
VCC
INPUT
I/O
2
3
1
24
23
22
21
20
19
18
17
16
15
14
13
VCC
INPUT
I/O
CLK1
INPUT
I/O
4
3
2
1
28 27 26
25
2
4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
5
I/O
I/O
I/O
I/O
I/O
I/O
NC
3
5
I/O
I/O
6
24
23
22
21
20
19
4
I/O
I/O
6
I/O
I/O
5
I/O
7
I/O
7
I/O
I/O
6
I/O
I/O
8
8
I/O
I/O
7
I/O
I/O
EP610
9
8
I/O
I/O
I/O
9
I/O
9
I/O
I/O
10
11
12
I/O
I/O
10
11
10
11
12
I/O
I/O
INPUT
GND
INPUT
CLK2
INPUT
CLK2
INPUT
GND
12 13 14 15 16 17 18
24-Pin SOIC
EP610
24-Pin DIP
28-Pin PLCC
EP610
EP610I
EP610
EP610I
Altera Corporation
755
ALTERA [ ALTERA CORPORATION ]
