Classic EPLD Family Data Sheet
EP610 devices have 16 macrocells, 4 dedicated input pins, 16 I/O pins,
General
Description
and 2 global clock pins (see Figure 8). Each macrocell can access signals
from the global bus, which consists of the true and complement forms of
the dedicated inputs and the true and complement forms of either the
output of the macrocell or the I/O input. The CLK1signal is a dedicated
global clock input for the registers in macrocells 9 through 16. The CLK2
signal is a dedicated global clock input for registers in macrocells 1
through 8.
Figure 8. EP610 Block Diagram
Numbers without parentheses are for DIP and SOIC packages. Numbers in parentheses are for J-lead packages.
2
1
(3)
(2)
INPUT
CLK1
INPUT (27) 23
CLK2 (16) 13
3
(4)
(5)
Macrocell 9
Macrocell 10
Macrocell 11
Macrocell 12
Macrocell 13
Macrocell 14
Macrocell 15
Macrocell 16
(26) 22
(25) 21
(24) 20
(23) 19
(22) 18
(21) 17
(20) 16
(18) 15
Macrocell 1
Macrocell 2
Macrocell 3
Macrocell 4
Macrocell 5
Macrocell 6
Macrocell 7
Macrocell 8
4
5
6
7
8
9
(6)
Global
Bus
(7)
(8)
(9)
(10)
10 (12)
INPUT (17) 14
11 (13) INPUT
Figure 9 shows the typical supply current (I ) versus frequency of EP610
CC
devices.
Figure 9. I vs. Frequency of EP610 Devices
CC
100
Turbo
10
Typical ICC
Active (mA)
V
CC = 5.0 V
TA = 25° C
1.0
0.1
Non-Turbo
1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 80 MHz
Frequency
756
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
