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DPCLK0 参数 Datasheet PDF下载

DPCLK0图片预览
型号: DPCLK0
PDF下载: 下载PDF文件 查看货源
内容描述: 的Cyclone III器件手册 [Cyclone III Device Handbook]
分类和应用:
文件页数/大小: 274 页 / 7302 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family  
5–33  
Spread-Spectrum Clocking  
Figure 5–24 shows the dynamic phase shifting waveform.  
Figure 5–24. Timing Diagram for Dynamic Phase Shift  
SCANCLK  
PHASESTEP  
PHASEUPDOWN  
PHASECOUNTERSELECT  
PHASEDONE  
a
b
c
d
PHASEDONE goes low  
synchronous with SCANCLK  
The PHASESTEPsignal is latched on the negative edge of SCANCLK(a,c) and must remain  
asserted for at least two SCANCLKcycles. Deassert PHASESTEPafter PHASEDONEgoes low.  
On the second SCANCLKrising edge (b,d) after PHASESTEPis latched, the values of  
PHASEUPDOWNand PHASECOUNTERSELECTare latched and the PLL starts dynamic  
phase-shifting for the specified counters, and in the indicated direction. PHASEDONEis  
deasserted synchronous to SCANCLKat the second rising edge (b,d) and remains low  
until the PLL finishes dynamic phase-shifting. Depending on the VCO and SCANCLK  
frequencies, PHASEDONElow time may be greater than or less than one SCANCLKcycle.  
You can perform another dynamic phase-shift after the PHASEDONEsignal goes from  
low to high. Each PHASESTEPpulse enables one phase shift. PHASESTEPpulses must be  
at least one SCANCLKcycle apart.  
f
For information about the ALTPLL_RECONFIG MegaWizard Plug-In Manager, refer  
to the Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction user  
guide.  
Spread-Spectrum Clocking  
The Cyclone III device family can accept a spread-spectrum input with typical  
modulation frequencies. However, the device cannot automatically detect that the  
input is a spread-spectrum signal. Instead, the input signal looks like deterministic  
jitter at the input of the PLL. Cyclone III device family PLLs can track a  
spread-spectrum input clock as long as it is in the input jitter tolerance specifications  
and the modulation frequency of the input clock is below the PLL bandwidth, which  
is specified in the fitter report. The Cyclone III device family cannot generate  
spread-spectrum signals internally.  
PLL Specifications  
f
For information about PLL specifications, refer to the Cyclone III Device Data Sheet and  
Cyclone III LS Device Data Sheet chapters.  
July 2012 Altera Corporation  
Cyclone III Device Handbook  
Volume 1  
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