Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
5–29
PLL Reconfiguration
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■
■
High time count = 2 cycles
Low time count = 1 cycle
rselodd= 1 effectively equals:
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High time count = 1.5 cycles
Low time count = 1.5 cycles
Duty cycle = (1.5/3)% high time count and (1.5/3)% low time count
Scan Chain Description
Cyclone III device family PLLs have a 144-bit scan chain.
Table 5–4 lists the number of bits for each component of the PLL.
Table 5–4. Cyclone III Device Family PLL Reprogramming Bits
Number of Bits
Block Name
Counter
Other
Total
18
18
18
18
18
18
18
9
(1)
(2)
C4
C3
C2
C1
C0
M
16
2
(2)
16
2
(2)
16
2
(2)
16
2
(2)
16
2
(2)
16
2
(2)
N
16
2
Charge Pump
9
0
0
(3)
Loop Filter
9
9
Total number of bits:
Notes to Table 5–4:
144
(1) LSB bit for C4 low-count value is the first bit shifted into the scan chain.
(2) These two control bits include rbypass, for bypassing the counter, and rselodd, to select the output clock duty
cycle.
(3) MSB bit for loop filter is the last bit shifted into the scan chain.
Figure 5–22 shows the scan chain order of the PLL components.
Figure 5–22. PLL Component Scan Chain Order
LF CP
N
M
C0
C1
DATAIN
MSB
LSB
C4
DATAOUT
C3
C2
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
ALTERA [ ALTERA CORPORATION ]
