5–30
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
PLL Reconfiguration
Figure 5–23 shows the scan chain bit order sequence for one PLL post-scale counter in
Cyclone III device family PLLs.
Figure 5–23. Scan Chain Bit Order
HB
8
HB
6
HB
5
HB
1
HB
3
HB
7
HB
9
HB
0
HB
2
HB
4
DATAIN
rbypass
rselodd
LB
5
LB
0
LB
1
LB
2
LB
3
LB
4
LB
6
LB
7
LB
8
LB
9
DATAOUT
f
For more information about the PLL scan chain, refer to the Implementing PLL
Reconfiguration in Cyclone III Devices application note.
Charge Pump and Loop Filter
You can reconfigure the charge pump and loop filter settings to update the PLL
bandwidth in real time. Table 5–5 through Table 5–7 list the possible settings for
charge pump (ICP), loop filter resistor (R), and capacitor (C) values for Cyclone III
device family PLLs.
Table 5–5. Charge Pump Bit Control
CP[2]
CP[1]
CP[0]
Setting (Decimal)
0
0
0
1
0
0
1
1
0
1
1
1
0
1
3
7
Table 5–6. Loop Filter Resistor Value Control
Setting
(Decimal)
LFR[4]
LFR[3]
LFR[2]
LFR[1]
LFR[0]
0
0
0
0
1
1
1
1
1
1
1
0
0
0
1
0
0
0
1
1
1
1
0
0
1
0
0
0
1
0
0
1
1
0
1
0
0
0
1
0
0
1
0
1
0
1
0
0
0
1
0
0
1
0
0
0
3
4
8
16
19
20
24
27
28
30
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
