5–32
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
PLL Reconfiguration
Table 5–9. Dynamic Phase Shifting Control Signals (Part 2 of 2)
Signal Name
Description
Source
Destination
PLL
reconfiguration
circuit
Logic array or I/O
pins
PHASESTEP
SCANCLK
Logic high enables dynamic phase shifting.
Free running clock from core used in
combination with PHASESTEPto enable or
disable dynamic phase shifting. Shared with
SCANCLKfor dynamic reconfiguration.
PLL
reconfiguration
circuit
GCLK or I/O pins
When asserted, it indicates to core logic that
the phase adjustment is complete and PLL is
ready to act on a possible second adjustment
pulse. Asserts based on internal PLL timing.
PLL reconfiguration Logic array or
circuit I/O pins
PHASEDONE
Deasserts on rising edge of SCANCLK
.
Table 5–10 lists the PLL counter selection based on the corresponding
PHASECOUNTERSELECTsetting.
Table 5–10. Phase Counter Select Mapping
PHASECOUNTERSELECT [2]
[1]
0
[0]
0
Selects
0
0
0
0
1
1
1
All Output Counters
M Counter
0
1
1
0
C0 Counter
C1 Counter
C2 Counter
C3 Counter
C4 Counter
1
1
0
0
0
1
1
0
To perform one dynamic phase shift step, you must perform the following
procedures:
1. Set PHASEUPDOWNand PHASECOUNTERSELECTas required.
2. Assert PHASESTEPfor at least two SCANCLKcycles. Each PHASESTEPpulse allows one
phase shift.
3. Deassert PHASESTEPafter PHASEDONEgoes low.
4. Wait for PHASEDONEto go high.
5. Repeat steps 1 through 4 as many times as required to perform multiple phase-
shifts.
PHASEUPDOWNand PHASECOUNTERSELECTsignals are synchronous to SCANCLKand must
meet the tsu and th requirements with respect to the SCANCLKedges.
1
You can repeat dynamic phase-shifting indefinitely. For example, in a design where
the VCO frequency is set to 1,000 MHz and the output clock frequency is set to
100 MHz, performing 40 dynamic phase shifts (each one yields 125 ps phase shift)
results in shifting the output clock by 180, in other words, a phase shift of 5 ns.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation