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DPCLK0 参数 Datasheet PDF下载

DPCLK0图片预览
型号: DPCLK0
PDF下载: 下载PDF文件 查看货源
内容描述: 的Cyclone III器件手册 [Cyclone III Device Handbook]
分类和应用:
文件页数/大小: 274 页 / 7302 K
品牌: ALTERA [ ALTERA CORPORATION ]
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3–12  
Chapter 3: Memory Blocks in the Cyclone III Device Family  
Memory Modes  
In true dual-port mode, you can access any memory location at any time from either  
port A or port B. However, when accessing the same memory location from both  
ports, you must avoid possible write conflicts. When you attempt to write to the same  
address location from both ports at the same time, a write conflict happens. This  
results in unknown data being stored to that address location. There is no conflict  
resolution circuitry built into the Cyclone III device family M9K memory blocks. You  
must handle address conflicts external to the RAM block.  
Figure 3–12 shows true dual-port timing waveforms for the write operation at port A  
and read operation at port B. Registering the outputs of the RAM simply delays the  
outputs by one clock cycle.  
q
Figure 3–12. Cyclone III Device Family True Dual-Port Timing Waveforms  
clk_a  
wren_a  
an  
a0  
a1  
a2  
a3  
a4  
a5  
address_a  
an-1  
a6  
din-1  
din  
din4  
din5  
din6  
data_a  
rden_a  
q_a (asynch)  
clk_b  
dout0  
dout1  
dout2  
din5  
dout3  
din4  
din  
din-1  
wren_b  
address_b  
rden_b  
bn  
b1  
b2  
b3  
b0  
q_b (asynch)  
doutn  
dout2  
dout0  
doutn-1  
dout1  
Shift Register Mode  
Cyclone III device family M9K memory blocks can implement shift registers for  
digital signal processing (DSP) applications, such as finite impulse response (FIR)  
filters, pseudo-random number generators, multi-channel filtering, and  
auto-correlation and cross-correlation functions. These and other DSP applications  
require local data storage, traditionally implemented with standard flipflops that  
quickly exhaust many logic cells for large shift registers. A more efficient alternative is  
to use embedded memory as a shift register block, which saves logic cell and routing  
resources.  
The size of a (w × m × n) shift register is determined by the input data width (w), the  
length of the taps (m), and the number of taps (n), and must be less than or equal to  
the maximum number of memory bits, which is 9,216 bits. In addition, the size of  
(w × n) must be less than or equal to the maximum width of the block, which is 36 bits.  
If you need a larger shift register, you can cascade the M9K memory blocks.  
Cyclone III Device Handbook  
Volume 1  
December 2011 Altera Corporation  
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