Chapter 3: Memory Blocks in the Cyclone III Device Family
3–9
Memory Modes
Figure 3–8 shows timing waveforms for read and write operations in single-port
mode with unregistered outputs. Registering the outputs of the RAM simply delays
the output by one clock cycle.
q
Figure 3–8. Cyclone III Device Family Single-Port Mode Timing Waveforms
clk_a
wren_a
rden_a
address_a
data_a
a0
B
a1
E
A
C
D
F
q_a (old data)
a0(old data)
A
B
B
C
a1(old data)
D
E
E
F
A
D
q_a (new data)
Simple Dual-Port Mode
Simple dual-port mode supports simultaneous read and write operations to different
locations. Figure 3–9 shows the simple dual-port memory configuration.
(1)
Figure 3–9. Cyclone III Device Family Simple Dual-Port Memory
data[]
rdaddress[]
rden
wraddress[]
wren
q[]
byteena[]
wr_addressstall
wrclock
rd_addressstall
rdclock
rdclocken
wrclocken
aclr
Note to Figure 3–9:
(1) Simple dual-port RAM supports input or output clock mode in addition to the read or write clock mode shown.
Cyclone III device family M9K memory blocks support mixed-width configurations,
allowing different read and write port widths.
Table 3–3 lists mixed-width configurations.
Table 3–3. Cyclone III Device Family M9K Block Mixed-Width Configurations (Simple Dual-Port Mode) (Part 1 of 2)
Write Port
Read Port
8192 × 1 4096 × 2 2048 × 4 1024 × 8 512 × 16 256 × 32 1024 × 9 512 × 18 256 × 36
8192 × 1
4096 × 2
2048 × 4
1024 × 8
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December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1
ALTERA [ ALTERA CORPORATION ]
