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DPCLK0 参数 Datasheet PDF下载

DPCLK0图片预览
型号: DPCLK0
PDF下载: 下载PDF文件 查看货源
内容描述: 的Cyclone III器件手册 [Cyclone III Device Handbook]
分类和应用:
文件页数/大小: 274 页 / 7302 K
品牌: ALTERA [ ALTERA CORPORATION ]
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3–14  
Chapter 3: Memory Blocks in the Cyclone III Device Family  
Clocking Modes  
Clocking Modes  
Cyclone III device family M9K memory blocks support the following clocking modes:  
Independent  
Input or output  
Read or write  
Single-clock  
When using read or write clock mode, if you perform a simultaneous read or write to  
the same address location, the output read data is unknown. If you require the output  
data to be a known value, use either single-clock mode or I/O clock mode and choose  
the appropriate read-during-write behavior in the MegaWizard Plug-In Manager.  
1
1
Violating the setup or hold time on the memory block input registers might corrupt  
the memory contents. This applies to both read and write operations.  
Asynchronous clears are available on read address registers, output registers, and  
output latches only.  
Table 3–5 lists the clocking mode versus memory mode support matrix.  
Table 3–5. Cyclone III Device Family Memory Clock Modes  
Simple  
True Dual-Port  
Mode  
Single-Port  
Mode  
Clocking Mode  
Dual-Port  
Mode  
ROM Mode  
FIFO Mode  
Independent  
Input or output  
Read or write  
Single-clock  
v
v
v
v
v
v
v
v
v
v
v
v
v
Independent Clock Mode  
Cyclone III device family M9K memory blocks can implement independent clock  
mode for true dual-port memories. In this mode, a separate clock is available for each  
port (port A and port B). clock Acontrols all registers on the port A side, while clock  
B
controls all registers on the port B side. Each port also supports independent clock  
enables for port A and B registers.  
I/O Clock Mode  
Cyclone III device family M9K memory blocks can implement input or output clock  
mode for FIFO, single-port, true, and simple dual-port memories. In this mode, an  
input clock controls all input registers to the memory block, including data, address,  
byteena, wren, and rdenregisters. An output clock controls the data-output registers.  
Each memory block port also supports independent clock enables for input and  
output registers.  
Cyclone III Device Handbook  
Volume 1  
December 2011 Altera Corporation  
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