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DPCLK0 参数 Datasheet PDF下载

DPCLK0图片预览
型号: DPCLK0
PDF下载: 下载PDF文件 查看货源
内容描述: 的Cyclone III器件手册 [Cyclone III Device Handbook]
分类和应用:
文件页数/大小: 274 页 / 7302 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 3: Memory Blocks in the Cyclone III Device Family  
3–11  
Memory Modes  
True Dual-Port Mode  
True dual-port mode supports any combination of two-port operations: two reads,  
two writes, or one read and one write, at two different clock frequencies. Figure 3–11  
shows the Cyclone III device family true dual-port memory configuration.  
(1)  
Figure 3–11. Cyclone III Device Family True Dual-Port Memory  
data_a[]  
address_a[]  
wren_a  
data_b[]  
address_b[]  
wren_b  
byteena_a[]  
addressstall_a  
clock_a  
byteena_b[]  
addressstall_b  
clock_b  
clocken_a  
rden_a  
clocken_b  
rden_b  
aclr_a  
aclr_b  
q_a[]  
q_b[]  
Note to Figure 3–11:  
(1) True dual-port memory supports input or output clock mode in addition to the independent clock mode shown.  
1
The widest bit configuration of the M9K blocks in true dual-port mode is 512 × 16-bit  
(18-bit with parity).  
Table 3–4 lists the possible M9K block mixed-port width configurations.  
Table 3–4. Cyclone III Device Family M9K Block Mixed-Width Configurations (True Dual-Port  
Mode)  
Write Port  
Read Port  
8192 × 1 4096 × 2 2048 × 4 1024 × 8 512 × 16 1024 × 9 512 × 18  
8192 × 1  
4096 × 2  
2048 × 4  
1024 × 8  
512 × 16  
1024 × 9  
512 × 18  
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In true dual-port mode, M9K memory blocks support separate wrenand rdensignals.  
You can save power by keeping the rdensignal low (inactive) when not reading.  
Read-during-write operations to the same address can either output “New Data” at  
that location or “Old Data”. To choose the desired behavior, set the Read-During-  
Write option to either New Data or Old Data in the RAM MegaWizard Plug-In  
Manager in the Quartus II software. For more information about this behavior, refer to  
“Read-During-Write Operations” on page 3–15.  
December 2011 Altera Corporation  
Cyclone III Device Handbook  
Volume 1  
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