Timing Model
Table 5–78. Maximum Output Toggle Rate on Stratix II Devices (Part 4 of 5)
Note (1)
Column I/O Pins (MHz)
Row I/O Pins (MHz) Clock Outputs (MHz)
Drive
Strength
I/O Standard
-3
-4
-5
-3
-4
-5
-3
-4
-5
1.8-V LVTTL
OCT 50 Ω
OCT 50 Ω
OCT 50 Ω
OCT 50 Ω
OCT 25 Ω
OCT 50 Ω
700
350
550
600
600
560
550
280
600
550
350
450
500
550
400
500
-
450
300
400
500
500
350
450
-
700
350
550
600
600
590
-
550
350
450
500
550
400
-
450
300
400
500
500
350
-
700
350
550
600
600
450
550
280
600
550
350
450
500
550
400
500
-
450
300
400
500
500
350
450
-
3.3-V LVCMOS
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II OCT 25 Ω
1.2-V HSTL (2)
OCT 50 Ω
OCT 50 Ω
-
-
-
1.5-V HSTL
Class I
550
500
600
550
500
550
500
1.8-V HSTL
Class I
OCT 50 Ω
OCT 25 Ω
OCT 50 Ω
OCT 25 Ω
OCT 50 Ω
OCT 25 Ω
650
500
600
600
560
550
650
500
600
600
500
500
550
400
500
600
500
550
600
450
500
500
350
450
600
450
500
650
-
600
-
600
-
650
500
600
600
560
550
650
500
600
600
500
500
550
400
500
600
500
550
600
450
500
500
350
450
600
450
500
1.8-V HSTL
Class II
Differential
SSTL-2 Class I
600
600
590
-
500
550
400
-
500
500
350
-
Differential
SSTL-2 Class II
Differential
SSTL-18 Class I
Differential
SSTL-18 Class II
1.8-V Differential OCT 50 Ω
HSTL Class I
650
-
600
-
600
-
1.8-V Differential OCT 25 Ω
HSTL Class II
1.5-V Differential OCT 50 Ω
600
550
500
HSTL Class I
5–72
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
