Timing Model
Table 5–77. Maximum Input Toggle Rate on Stratix II Devices (Part 2 of 2)
Dedicated Clock Inputs
(MHz)
Column I/O Pins (MHz)
Row I/O Pins (MHz)
Input I/O Standard
-3
-4
-5
-3
-4
-5
-3
-4
-5
1.8-V HSTL Class II
PCI (1)
500
500
500
280
500
500
500
500
-
500
450
450
-
500
500
500
500
500
500
280
500
500
500
500
-
500
400
400
-
-
-
-
-
-
-
-
-
-
-
-
-
PCI-X (1)
1.2-V HSTL (2)
Differential SSTL-2 Class I
500
500
500
500
(1), (3)
Differential SSTL-2 Class II
(1), (3)
500
500
500
500
500
500
500
-
500
500
500
500
500
500
500
-
500
500
500
500
500
500
500
-
-
-
-
500
500
500
500
500
500
500
717
500
500
500
500
500
500
500
717
500
500
500
500
500
500
500
640
Differential SSTL-18 Class I
(1), (3)
-
-
-
Differential SSTL-18 Class II
(1), (3)
-
-
-
1.8-V Differential HSTL
Class I (1), (3)
-
-
-
1.8-V Differential HSTL
Class II (1), (3)
-
-
-
1.5-V Differential HSTL
Class I (1), (3)
-
-
-
-
-
-
1.5-V Differential HSTL
Class II (1), (3)
HyperTransport technology
520
520
420
(4)
LVPECL (1)
LVDS (5)
-
-
-
-
-
-
-
-
-
-
520
-
-
520
-
-
420
-
450
717
450
450
717
450
400
640
400
LVDS (6)
Notes to Table 5–77:
(1) Row clock inputs don’t support PCI, PCI-X, LVPECL, and differential HSTL and SSTL standards.
(2) 1.2-V HSTL is only supported on column I/O pins.
(3) Differential HSTL and SSTL standards are only supported on column clock and DQS inputs.
(4) HyperTransport technology is only supported on row I/O and row dedicated clock input pins.
(5) These numbers apply to I/O pins and dedicated clock pins in the left and right I/O banks.
(6) These numbers apply to dedicated clock pins in the top and bottom I/O banks.
5–68
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
