DC & Switching Characteristics
Table 5–78. Maximum Output Toggle Rate on Stratix II Devices (Part 5 of 5)
Note (1)
Column I/O Pins (MHz)
Row I/O Pins (MHz) Clock Outputs (MHz)
Drive
Strength
I/O Standard
-3
-4
-5
-3
-4
-5
-3
-4
-5
1.2-V Differential OCT 50 Ω
280
-
-
-
-
-
280
-
-
HSTL
Notes to Table 5–78:
(1) The toggle rate applies to 0-pF output load for all I/O standards except for LVDS and HyperTransport technology
on row I/O pins. For LVDS and HyperTransport technology on row I/O pins, the toggle rates apply to load from
0 to 5pF.
(2) 1.2-V HSTL is only supported on column I/O pins in I/O banks 4, 7, and 8.
(3) Differential HSTL and SSTL is only supported on column clock and DQS outputs.
(4) HyperTransport technology is only supported on row I/O and row dedicated clock input pins.
(5) LVPECL is only supported on column clock pins.
(6) Refer to Tables 5–81 through 5–91 if using SERDES block. Use the toggle rate values from the clock output column
for PLL output.
Table 5–79. Maximum Output Clock Toggle Rate Derating Factors (Part 1 of 5)
Maximum Output Clock Toggle Rate Derating Factors (ps/pF)
Drive
Strength
I/O Standard
Column I/O Pins
Row I/O Pins
-4
Dedicated Clock Outputs
-3
-4
-5
-3
-5
-3
-4
-5
3.3-V LVTTL
4 mA
8 mA
478
260
213
136
138
134
377
206
141
108
83
510
333
247
197
187
177
391
212
145
111
88
510
333
247
197
187
177
391
212
145
111
88
478
510
510
466
291
211
166
154
143
377
178
115
86
510
333
247
197
187
177
391
212
145
111
88
510
333
247
197
187
177
391
212
145
111
88
260
333
333
12 mA
16 mA
20 mA
24 mA
4 mA
213
247
247
-
-
-
-
-
-
-
377
206
-
-
391
212
-
-
391
212
-
3.3-V LVCMOS
8 mA
12 mA
16 mA
20 mA
24 mA
4 mA
-
-
-
-
-
-
79
65
72
72
-
-
-
74
72
72
2.5-V
LVTTL/LVCMOS
387
163
142
120
427
224
203
182
427
224
203
182
387
163
142
-
427
224
203
-
427
224
203
-
391
170
152
134
427
224
203
182
427
224
203
182
8 mA
12 mA
16 mA
Altera Corporation
April 2011
5–73
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
