Clock Modes
Figure 2–15. Stratix II and Stratix II GX Input/Output Clock Mode in Single-Port Mode
Note (1)
6 LAB Row
Clocks
Memory Block
6
256 ´ 16
data[ ]
address[ ]
byteena[ ]
D
ENA
Q
Q
Q
Data In
512 ´ 8
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
Address
D
ENA
To MultiTrack
Interconnect (2)
Data Out
Byte Enable
D
Q
ENA
D
ENA
Address
Clock Enable
addressstall
wren
Write Enable
outclocken
Write
Pulse
Generator
D
ENA
Q
inclocken
inclock
outclock
Notes to Figure 2–15:
(1) Violating the setup or hold time on the memory block address registers could corrupt the memory contents. This
applies to both read and write operations.
(2) Refer to the Stratix II Device Family Data Sheet (volume 1) of the Stratix II Device Handbook or the Stratix II GX Device
Family Data Sheet (volume 1) of the Stratix II GX Device Handbook for more information on the MultiTrack
interconnect.
Read/Write Clock Mode
Stratix II and Stratix II GX TriMatrix memory blocks can implement
read/write clock mode for simple dual-port memory. This mode uses up
to two clocks. The write clock controls the blocks’ data inputs, write
address, and write enable signals. The read clock controls the data output,
read address, and read enable signals. The memory blocks support
independent clock enables for each clock for the read- and write-side
registers. Asynchronous clear signals for the registers, however, are not
supported. Figure 2–16 shows a memory block in read/write clock mode.
2–26
Altera Corporation
January 2008
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
