TriMatrix Embedded Memory Blocks in Stratix II and Stratix II GX Devices
bits for the M512 block, 36 bits for the M4K block, and 144 bits for the
MRAM block. If a larger shift register is required, the memory blocks can
be cascaded.
In M512 and M4K blocks, data is written into each address location at the
falling edge of the clock and read from the address at the rising edge of
the clock. The shift-register mode logic automatically controls the
positive and negative edge clocking to shift the data in one clock cycle.
The MRAM block performs reads and writes on the rising edge.
Figure 2–11 shows the TriMatrix memory block in the shift-register mode.
Figure 2–11. Stratix II and Stratix II GX Shift-Register Memory Configuration
w × m × n Shift Register
m-Bit Shift Register
W
W
m-Bit Shift Register
W
W
n Number of Taps
m-Bit Shift Register
W
W
m-Bit Shift Register
W
W
Altera Corporation
January 2008
2–19
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
