TriMatrix Embedded Memory Blocks in Stratix II and Stratix II GX Devices
Figure 2–8. Stratix II and Stratix II GX Simple Dual-Port Timing Waveforms
wrclock
wren
a0
a1
a2
a3
a4
a5
an
din
wraddress
data (1)
rdclock
an-1
a6
din-1
din4
din5
din6
rden (2)
rdaddress
bn
doutn-2
b1
b2
b3
b0
q (synch)
doutn-1
doutn
dout0
doutn
q (asynch)
dout0
doutn-1
Notes to Figure 2–8:
(1) The crosses in the datawaveform during read mean “don’t care.”
(2) The read enable rdensignal is not available in M-RAM blocks. The M-RAM block in simple dual-port mode always
reads out the data stored at the current read address location.
True Dual-Port Mode
Stratix II and Stratix II GX M4K and M-RAM memory blocks support the
true dual-port mode. True dual-port mode supports any combination of
two-port operations: two reads, two writes, or one read and one write at
two different clock frequencies. Figure 2–9 shows Stratix II and
Stratix II GX true dual-port memory configuration.
Figure 2–9. Stratix II and Stratix II GX True Dual-Port Memory Note (1)
data_a[]
address_a[]
wren_a
data_b[]
address_b[]
wren_b
byteena_a[]
addressstall_a
clock_a
byteena_b[]
addressstall_b
clock_b
enable_a
aclr_a
enable_b
aclr_b
q_a[]
q_b[]
Note to Figure 2–9:
(1) True dual-port memory supports input/output clock mode in addition to the
independent clock mode shown.
Altera Corporation
January 2008
2–15
Stratix II Device Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
