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CLK12P 参数 Datasheet PDF下载

CLK12P图片预览
型号: CLK12P
PDF下载: 下载PDF文件 查看货源
内容描述: 的Stratix II器件手册,卷1 [Stratix II Device Handbook, Volume 1]
分类和应用:
文件页数/大小: 768 页 / 5210 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Memory Modes  
The widest bit configuration of the M4K and M-RAM blocks in true dual-  
port mode is as follows:  
256 × 16-bit (×18-bit with parity) (M4K)  
8K × 64-bit (×72-bit with parity) (M-RAM)  
The 128 × 32-bit (×36-bit with parity) configuration of the M4K block and  
the 4K × 128-bit (×144-bit with parity) configuration of the M-RAM block  
are unavailable because the number of output drivers is equivalent to the  
maximum bit width of the respective memory block. Because true  
dual-port RAM has outputs on two ports, the maximum width of the true  
dual-port RAM equals half of the total number of output drivers.  
Table 2–12 lists the possible M4K block mixed-port width configurations.  
Table 2–12. Stratix II and Stratix II GX M4K Block Mixed-Port Width Configurations (True Dual-Port)  
Write Port  
1K × 4 512 × 8 256 × 16  
Read Port  
4K × 1  
2K × 2  
512 × 9  
256 × 18  
4K × 1  
2K × 2  
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
1K × 4  
512 × 8  
256 × 16  
512 × 9  
256 × 18  
v
v
v
v
Table 2–13 lists the possible M-RAM block mixed-port width  
configurations.  
Table 2–13. Stratix II and Stratix II GX M-RAM Block Mixed-Port Width  
Configurations (True Dual-Port)  
Write Port  
Read Port  
64K × 9  
32K × 18  
18K × 36  
8K × 72  
v
64K × 9  
32K × 18  
18K × 36  
8K × 72  
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
2–16  
Stratix II Device Handbook, Volume 2  
Altera Corporation  
January 2008  
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