Reconfigurable Bandwidth
■
Disable the system during switchover if it is not tolerant to frequency
variations during the PLL resynchronization period. There are two
ways to disable the system. First, the system may require some time
to stop before switchover occurs. The switchover circuitry includes
an optional five-bit counter to delay when the reference clock is
switched. You have the option to control the time-out setting on this
counter (up to 32 cycles of latency) before the clock source switches.
You can use these cycles for disaster recovery. The clock output
frequency varies slightly during those 32 cycles since the VCO can
still drift without an input clock. Programmable bandwidth can
control the PLL response to limit drift during this 32 cycle period.
A second option available is the ability to use the PFD enable signal
(pfdena) along with user-defined control logic. In this case you can
use clk0_badand clk1_badstatus signals to turn off the PFD so
the VCO maintains its last frequency. You can also use the state
machine to switch over to the secondary clock. Upon re-enabling the
PFD, output clock enable signals (clkena) can disable clock outputs
during the switchover and resynchronization period. Once the lock
indication is stable, the system can re-enable the output clock(s).
■
Stratix II and Stratix II GX enhanced and fast PLLs provide advanced
control of the PLL bandwidth using the PLL loop’s programmable
characteristics, including loop filter and charge pump.
Reconfigurable
Bandwidth
Background
PLL bandwidth is the measure of the PLL’s ability to track the input clock
and jitter. The closed-loop gain 3-dB frequency in the PLL determines the
PLL bandwidth. The bandwidth is approximately the unity gain point for
open loop PLL response. As Figure 1–26 shows, these points correspond
to approximately the same frequency.
1–44
Altera Corporation
Stratix II Device Handbook, Volume 2
July 2009
ALTERA [ ALTERA CORPORATION ]
